This invention relates to clock signal generation for an integrated circuit.
A clock on an integrated circuit is often distributed over a network that imposes a significant delay to the clock, but that yields synchronization of the distributed clock at remote nodes of the network. For example, a tree structure may be used for such clock distribution. In some systems, the clock is generated such that it is synchronized with an external reference clock at the leaves of the network.
It may be desirable to divide the clock to reduce the clocking rate of circuitry, for example, to reduce power consumption. However, such clock frequency division may result in the clock not being suitably synchronized with the external clock reference.